This invention relates to arrays of electrically erasable EPROM cells, and particularly to techniques for erasing such arrays.
Erasable programmable read-only memory (EPROM) technology is well known for use in both memory and programmable logic applications. In particular, EPROMs are implemented using floating gate field effect transistors in which the binary states of the EPROM cell are represented by the presence or absence on the floating gate of sufficient charge to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
EPROMs are available in several varieties. In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs can be referred to as ultraviolet erasable programmable read-only memories ("UVEPROMs"). UVEPROMs are programmed by running a high current between the drain and the source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic ("hot") electrons from the drain-to-source current, which jump onto the floating gate in an attempt to reach the gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory ("EEPROM" or"E.sup.2 PROM"). EEPROMs are programmed and erased electrically using a phenomenon known as Fowler-Nordheim tunneling.
Still another form of EPROM is "Flash EPROM," which is programmed using hot electrons like a traditional EPROM (UVEPROM) and electrically erased using Fowler-Nordheim tunneling like an EEPROM. Both Flash EPROM and EEPROM, which can be erased in a "flash" or bulk mode in which all cells in an array can be erased simultaneously using Fowler-Nordheim tunneling, and will be referred to hereinafter as "Flash cells" or "Flash devices."
UVEPROM and EEPROM have been used for both memory applications and programmable logic applications. To date, however, Flash devices have been used primarily for memory applications. One obstacle to using Flash devices is the phenomenon of overerasure. Overerasure is the result of continuing the Fowler-Nordheim erase process too long, so that too much charge is removed from the floating gate, with the result that the Flash device goes into depletion mode, in which it is always conducting (unless the gate-to-source voltage goes negative).
In a programmable logic device ("PLD") or memory chip in which there is an overerased Flash transistor, the leakage current resulting from the depletion mode operation of that transistor can interfere with accurate reading of the states of neighboring cells in the array. This can be cured by having in each cell a second "select" transistor, allowing the selection or deselection of a particular device for reading. Many Flash memory applications employ such select transistors. However, in logic applications, the use of such a transistor consumes chip area, and also affects array speed.
Another solution frequently employed with Flash EPROM devices is to use an "intelligent" erasing algorithm in which the device is repeatedly erased a small amount and then verified to see if the cell threshold has shifted the desired amount. However, such a technique can be time-consuming, and adds to programming complexity.
In copending, commonly-assigned U.S. patent application Ser. No. 07/788,607, filed concurrently herewith and hereby incorporated by reference in its entirety, a technique is disclosed for erasing entire columns or arrays of Flash devices simultaneously while preventing overerasure. That is accomplished by programming all devices in the column or array so that none of them conduct, and then connecting them to a high voltage erase supply through a high-impedance device. As the Flash devices erase, one will eventually begin to conduct. As soon as that happens, a current will flow through the conducting Flash device and the high-impedance device, dividing the high voltage supply so that the potential across the Flash devices is no longer high enough to support Fowler-Nordheim tunneling, and erasure of all Flash devices in the column or array stops. Erasure is therefore self-limiting. A drawback of that technique, however, is that erasure of all devices stops when the first device conducts. One must rely on a tight distribution of device characteristics among all the devices in the column or array to be sure that the remaining devices are also erased.
Accordingly, it would be desirable to be able to provide programming methods or apparatus for groups of Flash cells in which susceptibility to overerasure is reduced or eliminated, and in which erasure of each device in the group could be more readily assured.